1. Field of the Invention
The present invention relates generally to programmable integrated circuits and computer systems, and more particularly, to floating point units (“FPU”) with programmable fabric.
2. Description of Related Art
Highly mathematical intensive applications are desirable to provide the necessary computing powers in modern systems. Mathematical computations that require complex mathematical equations, very large numbers, or high precision are frequently referred to as floating point calculations. Floating-point numbers are commonly represented as a concatenation of three parts: a sign bit, an exponent field, and a significant field (also known as a mantissa). A well-know industrial standard for floating point numbers and calculations published by the Institute of Electrical and Electronic Engineers (IEEE) is the ANSI/IEEE Standard 754 (1985, reaffirmed 1990), the Standard for Binary Floating Point Arithmetic. As an example of a floating point parameter defined by IEEE, a single precision floating point number has a 23-bit mantissa field, an 8-bit exponent field, and a 1-bit sign field. The most significant bit of the mantissa is not represented such that the most significant bit of the mantissa assumes a value of 1, except for denormal numbers whose most significant bit of the mantissa is zero.
Field programmable gate arrays are often selected by design engineers to provide a flexible approach in programming and re-programming integrated circuits in order to accommodate a system specification, correct errors in the system, or make improvements to the system by reprogramming the FPGA. One conventional field programmable gate array architecture is implemented by using groups of look-up tables and programmable interconnect circuits. While the look-up tables and sequential elements are connected to each other, the connections to the groups of look-up tables typically originate from a switchbox located in each group of the look-up table. A hierarchical interconnect structure connects to elements in a look-up table through a switchbox, thereby serving as the primary source of connecting look-up tables from one logic block to another logic block. The inputs to the look-up tables are therefore generated primarily from the switchbox. The look-up table outputs are directly fed to other look-up tables as well as the elements within the look-up tables, but the connections to other look-up tables' inputs are made through the switchbox.
In another conventional structure, a majority of the inputs required for performing all functionality of configurable logic blocks are typically restricted to inputs associated with a particular configurable logic block, other than through the use of the switch box. The same is true for outputs of a particular configurable logic block which are restricted to within the configurable logic block other than through the use of the switch box. A key building block in a programmable logic circuit is the design of a configurable logic block.
With advances in industrial applications, it is desirable to design a program logic chip that provides a configurable floating point unit with programmable logic and routing fabric.